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getting_started_example [2019/03/22 12:02] – ba | getting_started_example [2021/09/14 16:10] – [Getting startet example] ba | ||
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====== Getting startet example ====== | ====== Getting startet example ====== | ||
- | Load the example | + | The ZSOM SDK comes with a variety of examples for all available targets. |
+ | Refer to [[zsom: | ||
+ | |||
+ | ===== Components ===== | ||
+ | The getting started example consists of code for the components listed below.\\ | ||
+ | The FPGA bitfile is precompiled and enables for use without LabVIEW FPGA.\\ | ||
+ | The example | ||
+ | |||
+ | ==== DIO ==== | ||
+ | |||
+ | The digital IO lines are controlled trough integer controls on the FPGA interface. One bit stands for a specific input, output or direction line. The integer values are built using the boolean array to integer conversion. The IOs are forwareded trough the FPGA and can all be controlled in the RT application. | ||
+ | See [[zsom: | ||