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gpio_3o5v [2019/09/24 11:09]
ba [Features]
gpio_3o5v [2019/09/24 11:20] (current)
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 {{:​snippets:​dio.init.io_olh.png?​direct|}} {{:​snippets:​dio.init.io_olh.png?​direct|}}
 {{:​snippets:​dio.init.io.png?​direct&​400|}} {{:​snippets:​dio.init.io.png?​direct&​400|}}
 +===== >20Mhz =====
 +Since the FPGA code per default runs at 40Mhz. Output frequencies > 20Mhz are not possible in the default clock domain.\\
 +You can run code inside of single cycle timed loops on faster clock rates.\\
 +One FPGA IO can only be used in one clock domain. This can be acheived in the following way:\\
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